The terminals of a standard chip capacitor (e.g. ceramic or metalized stacked film) are comprised primary of surface conductors on opposite ends of the capacitor body. Each terminal may cover the end and may extend slightly around one or more edges (e.g. top, bottom and sides) towards the opposite terminal. The interfacial attachment area of an assembled chip capacitor is limited to the intersection of its terminal area on the bottom side of the capacitor and the mating capacitor footprint of its host substrate. This interface area is typically insufficient for a good electrical and mechanical connection. To compensate for this, the attach pads of the capacitor footprint extend beyond the length and width of the capacitor end terminals to allow formation of peripheral solder fillets up the sides and ends of the terminals. These fillets increase the capacitor solder attach area sufficiently for good electrical and mechanical connection to its host substrate. However, the use of solder fillets to increase the capacitor solder area are prone to tomb-stoning. Tomb-stoning occurs when a chip component becomes partially or completely lifted off one end of the surface of a bonding pad of an integrated circuit. Tomb-stoning typically occurs from surface tension in the end fillets during solder reflow attach processes. Moreover, the use of solder fillets extends the area needed for the chip capacitor.
In addition, each internal conductor plate of a standard chip capacitor is connected along one edge of its periphery to one end surface terminals. Most standard Electronic Industries Alliance (EIA) size chip capacitors terminate each plate along one narrow edge, giving the capacitor body and its plates a forward length-to-width aspect ratio (length/width>1). Capacitor and plate length is defined here as the terminal to terminal dimension. Some non-standard chip capacitors terminate each plate along a width edge, giving the capacitor and its plates a reverse aspect ratio (length/width<1). A capacitor's equivalent series inductance (ESL) and equivalent series resistance (ESR) is proportional to its plate aspect ratio. A lower plate aspect ratio results in lower ESL and ESR as well as better capacitor performance.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a chip capacitor that has an improved interfacial attachment area and an improved effective plate aspect ratio.